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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
D D
Direct Upgrades to TL07x and TL08x BiFET Operational Amplifiers Faster Slew Rate (20 V/s Typ) Without Increased Power Consumption
TL051 D OR P PACKAGE (TOP VIEW)
D
On-Chip Offset-Voltage Trimming for Improved DC Performance and Precision Grades Are Available (1.5 mV, TL051A)
TL052 D, P, OR PS PACKAGE (TOP VIEW)
TL054 D, DB, N, OR NS PACKAGE (TOP VIEW)
OFFSET N1 IN- IN+ VCC-
1 2 3 4
8 7 6 5
NC VCC+ OUT OFFSET N2
1OUT 1IN- 1IN+ VCC-
1 2 3 4
8 7 6 5
VCC+ 2OUT 2IN- 2IN+
1OUT 1IN- 1IN+ VCC+ 2IN+ 2IN- 2OUT
1 2 3 4 5 6 7
14 13 12 11 10 9 8
4OUT 4IN- 4IN+ VCC- 3IN+ 3IN- 3OUT
description/ordering information
The TL05x series of JFET-input operational amplifiers offers improved dc and ac characteristics over the TL07x and TL08x families of BiFET operational amplifiers. On-chip Zener trimming of offset voltage yields precision grades as low as 1.5 mV (TL051A) for greater accuracy in dc-coupled applications. Texas Instruments improved BiFET process and optimized designs also yield improved bandwidth and slew rate without increased power consumption. The TL05x devices are pin-compatible with the TL07x and TL08x and can be used to upgrade existing circuits or for optimal performance in new designs. BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors, without sacrificing the output drive associated with bipolar amplifiers. This makes them better suited for interfacing with high-impedance sensors or very low-level ac signals. They also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption. The TL05x family was designed to offer higher precision and better ac response than the TL08x, with the low noise floor of the TL07x. Designers requiring significantly faster ac response or ensured lower noise should consider the Excalibur TLE208x and TLE207x families of BiFET operational amplifiers. Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to observe common-mode input voltage limits and output swing when operating from a single supply. DC biasing of the input signal is required, and loads should be terminated to a virtual-ground node at mid-supply. Texas Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from single supplies. The TL05x are fully specified at 15 V and 5 V. For operation in low-voltage and/or single-supply systems, Texas Instruments LinCMOS families of operational amplifiers (TLC-prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to the slew rate and bandwidth requirements, and also the output loading.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
ORDERING INFORMATION
TA VIOmax AT 25C PDIP (P) 800 V SOIC (D) PACKAGE Tube of 50 Tube of 75 Tube of 75 Reel of 2500 PDIP (P) PDIP (N) Tube of 50 Tube of 25 Tube of 75 0C to 70C Reel of 2500 1.5 mV SOIC (D) Tube of 75 Reel of 2500 Tube of 50 Reel of 2500 SOP (PS) SSOP (DB) PDIP (N) 4 mV SOIC (D) SOP (NS) PDIP (P) 800 V SOIC (D) PDIP (N) PDIP (P) -40C to 85C 40C 1.5 1 5 mV SOIC (D) Reel of 2000 Reel of 2000 Tube of 25 Tube of 50 Reel of 2500 Reel of 2000 Tube of 50 Tube of 75 Reel of 2500 Tube of 25 Tube of 50 Tube of 75 Tube of 75 Reel of 2500 Tube of 50 Reel of 2500 PDIP (N) 4 mV SOIC (D) Tube of 25 Tube of 50 Reel of 2500 ORDERABLE PART NUMBER TL051ACP TL052ACP TL051ACD TL052ACD TL052ACDR TL051CP TL052CP TL054ACN TL051CD TL051CDR TL052CD TL052CDR TL054ACD TL054ACDR TL052CPSR TL054CDBR TL054CN TL054CD TL054CDR TL054CNSR TL052AIP TL052AID TL052AIDR TL054AIN TL051IP TL052IP TL051ID TL052ID TL052IDR TL054AID TL054AIDR TL054IN TL054ID TL054IDR TOP-SIDE MARKING TL051ACP TL052ACP 051AC 052AC TL051CP TL052CP TL054ACN TL051C TL052C TL054C TL052 TL054 TL054CN TL054C TL054 TL052AI 052AI TL054AIN TL051IP TL052IP TL051I TL052I TL054AI TL054IN TL054I
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
symbol (each amplifier)
- OUT IN+ + VCC+ Q10 Q2 Q3 Q6 Q11 IN+ D1 IN- JF1 Q4 Q1 See Note A OFFSET N1 OFFSET N2 R1 R2 R3 Q5 R4 R6 Q8 Q9 R10 D2 JF2 C1 Q14 Q17 R5 R8 Q12 Q13 R7 R9 OUT Q7 Q16 Q15 JF3 VCC- NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL051x. ACTUAL DEVICE COMPONENT COUNT COMPONENT Transistors Resistors Diodes Capacitors TL051 20 10 2 1 TL052 34 19 3 2 TL054 62 37 5 4 IN-
equivalent schematic (each amplifier)
These figures include all four amplifiers and all ESD, bias, and trim circuitry.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Supply voltage, VCC- (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 V Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V Input voltage range, VI (any input, see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 mA Total current into VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA Total current out of VCC- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA Duration of short-circuit current at (or below) 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Package thermal impedance, JA (see Notes 4 and 5): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 97C/W D package (14 pin) . . . . . . . . . . . . . . . . . . . . . 86C/W DB package (14 pin) . . . . . . . . . . . . . . . . . . . 96C/W N package (14 pin) . . . . . . . . . . . . . . . . . . . . . 80C/W NS package (14 pin) . . . . . . . . . . . . . . . . . . . 76C/W P package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 85C/W PS package (8 pin) . . . . . . . . . . . . . . . . . . . . 95C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Lead temperature 1,6 mm (1/16inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC-. 2. Differential voltages are at IN+ with respect to IN-. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/JA. Operating at the absolute maximum TJ of 150C can impact reliability. 5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
C SUFFIX MIN VCC VIC TA Supply voltage Common mode input voltage Common-mode Operating free-air temperature VCC = 5 V VCC = 15 V 5 -1 -11 0 MAX 15 4 11 70 I SUFFIX MIN 5 -1 -11 -40 MAX 15 4 11 85 UNIT V V C
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL051C and TL051AC electrical characteristics at specified free-air temperature
TL051C, TL051AC PARAMETER TEST CONDITIONS TA 25C Full range 25C Full range 25C to 70C 25C to 70C 25C VO = 0, VIC = 0, See Figure 5 VO = 0, VIC = 0, See Figure 5 25C 70C 25C 70C 25C VICR Common-mode input voltage range Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C AVD ri ci CMRR Large-signal differential L i l diff ti l amplification voltage am lification Input resistance Input capacitance Common-mode Common mode rejection ratio VIC = VICRmin, min 0, VO = 0 RS = 50 RL = 2 k 0C 70C 25C 25C 25C 0C 70C 25C kSVR Supply voltage rejection Supply-voltage ratio (VCC/VIO) VO = 0, RS = 50 0C 70C 25C ICC Supply current y VO = 0, No load 0C 70C 65 65 65 75 75 75 -1 to 4 -1 to 4 3 3 2.5 2.5 -2.5 -2.5 -2.3 -2.3 25 30 20 59 65 46 1012 10 85 84 84 99 98 97 2.6 2.7 2.6 3.2 3.2 3.2 75 75 75 75 75 75 -3.2 -3.5 3.8 4.2 8 8 0.04 4 0.02 20 0.15 -2.3 to 5.6 100 1 200 4 -11 to 11 -11 to 11 13 13 11.5 11.5 -12 -12 -11 -11 50 60 30 105 129 85 1012 12 93 92 91 99 98 97 2.7 2.8 2.7 3.2 3.2 3.2 mA dB dB V/mV pF -12 -13.2 V 12.7 13.9 V 0.55 VCC = 5 V MIN TYP MAX 0.75 3.5 4.5 2.8 3.8 8 V/C 8 0.04 5 0.025 30 0.2 -12.3 to 15.6 100 1 200 4 25 V/mo pA nA pA nA 0.35 VCC = 15 V MIN TYP MAX 0.59 1.5 2.5 0.8 1.8 mV UNIT
TL051C VIO Input offset voltage TL051AC VO = 0 0, VIC = 0, RS = 50 TL051C TL051AC
aV
IO
Temperature coefficient of input offset voltage Input offset-voltage long-term drift
IIO IIB
Input offset current Input bias current
V
VOM OM+
Maximum positive peak output voltage swing
RL = 10 k RL = 2 k RL = 10 k RL = 2 k
VOM OM-
Maximum negative peak g output voltage swing
Full range is 0C to 70C. This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150C, extrapolated to TA = 25C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. For VCC = 5 V, VO = 2.3 V, or for VCC = 15 V, VO = 10 V.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL051C and TL051AC operating characteristics at specified free-air temperature
TL051C, TL051AC PARAMETER TEST CONDITIONS TA 25C SR+ Positive l P iti slew rate t at unity gain RL = 2 k, , See Figure 1 SR- Negative slew rate N ti l t at unity gain CL = 100 pF, , Full range 25C Full range 25C tr Rise time VI(PP) = 10 mV, RL = 2 k, k CL = 100 pF F, See Figures 1 and 2 g 0C 70C 25C 0C 70C 25C Overshoot factor f = 10 Hz RS = 20 , See Figure 3 f = 1 kHz f = 10 Hz to 10 kHz 0C 70C Vn VN(PP) In THD Equivalent input noise q voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current Total harmonic distortion 25C 25C 25C 25C RL = 2 k, 25C 25C B1 Unity-gain bandwidth VI = 10 mV, V CL = 25 pF F, RL = 2 k, k See Figure 4 0C 70C 25C m Phase margin at unity gain VI = 10 mV, mV F, CL = 25 pF, RL = 2 k, k See Figure 4 0C 70C tf Fall time VCC = 5 V MIN TYP MAX 16 16.4 15 16 55 54 63 55 54 62 24 24 24 75 18 4 0.01 0.003 3 3.2 2.7 59 58 59 VCC = 15 V MIN TYP MAX 13 11 13 11 20 22.6 18 19.3 56 55 63 57 56 64 19 19 19 75 18 4 0.01 0.003 3.1 3.3 2.8 62 62 62 deg MHz 30 nV/Hz V pA/Hz % % ns V/s UNIT
f = 1 kHz RS = 1 k, f = 1 kHz
Full range is 0C to 70C. For VCC = 5 V, VI(PP) = 1 V; for VCC = 15 V, VI(PP) = 5 V. This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. For VCC = 5 V, VO(RMS) = 1 V; for VCC = 15 V, VO(RMS) = 6 V.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL051I and TL051AI electrical characteristics at specified free-air temperature
TL051I, TL051AI PARAMETER TEST CONDITIONS TA 25C Full range 25C Full range 25C to 85C 25C to 85C 25C VO = 0, VIC = 0, See Figure 5 VO = 0, VIC = 0, See Figure 5 25C 85C 25C 85C 25C VICR Common-mode input voltage range Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C AVD ri ci CMRR Large-signal differential L i l diff ti l amplification voltage am lification Input resistance Input capacitance Common mode Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 VO = 0, 0 RS = 50 RL = 2 k -40C 85C 25C 25C 25C -40C 85C 25C kSVR Supply-voltage Supply voltage rejection ratio (VCC/VIO) -40C 85C 25C ICC Supply current VO = 0, No load -40C 65 65 65 75 75 75 -1 to 4 -1 to 4 3 3 2.5 2.5 -2.5 -2.5 -2.3 -2.3 25 30 20 59 74 43 1012 10 85 83 84 99 98 99 2.6 2.4 3.2 3.2 75 75 75 75 75 75 -3.2 -3.5 3.8 4.2 7 8 0.04 4 0.06 20 0.6 -2.3 to 5.6 100 10 200 20 -11 to 11 -11 to 11 13 13 11.5 11.5 -12 -12 -11 -11 50 60 30 105 145 76 1012 12 93 90 93 99 98 99 2.7 2.6 3.2 3.2 mA dB dB V/mV pF -12 -13.2 V 12.7 13.9 V 0.55 VCC = 5 V MIN TYP MAX 0.75 3.5 5.3 2.8 4.6 8 V/C 8 0.04 5 0.07 30 0.7 -12.3 to 15.6 100 10 200 20 25 V/mo pA nA pA nA 0.35 VCC = 15 V MIN TYP MAX 0.59 1.5 3.3 0.8 2.6 mV UNIT
TL051I VIO Input offset voltage TL051AI VO = 0 0, VIC = 0, RS = 50 TL051I TL051AI
aV
IO
Temperature coefficient of input offset voltage Input offset-voltage long-term drift
IIO IIB
Input offset current Input bias current
V
VOM +
Maximum positive peak output voltage swing
RL = 10 k RL = 2 k RL = 10 k RL = 2 k
VOM -
Maximum negative peak g output voltage swing
85C 2.5 3.2 2.6 3.2 Full range is -40C to 85C This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150C, extrapolated to TA = 25C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. For VCC = 5 V, VO = 2.3 V, or for VCC = 15 V, VO = 10 V.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL051I and TL051AI operating characteristics at specified free-air temperature
TL051I, TL051AI PARAMETER TEST CONDITIONS TA 25C SR+ Positive l P iti slew rate t at unity gain RL = 2 k, , See Figure 1 SR- Negative slew rate N ti l t at unity gain CL = 100 pF, , Full range 25C Full range 25C tr Rise time VI(PP) = 10 mV, () RL = 2 k, k CL = 100 pF F, See Figures 1 and 2 g -40C 85C 25C -40C 85C 25C Overshoot factor f = 10 Hz RS = 20 , See Figure 3 f = 1 kHz f = 10 Hz to 10 kHz -40C 85C Vn VN(PP) In THD Equivalent input noise q voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current Total harmonic distortion 25C 25C 25C 25C RL = 2 k, 25C 25C B1 Unity-gain bandwidth VI = 10 mV, V CL = 25 pF F, RL = 2 k, k See Figure 4 -40C 85C 25C m Phase margin at unity gain VI = 10 mV, mV F, CL = 25 pF, RL = 2 k, k See Figure 4 -40C 85C tf Fall time 55 52 64 55 51 64 24 24 24 75 18 4 0.01 0.003 3 3.5 2.6 59 58 59 15 VCC = 5 V MIN TYP MAX 16 VCC = 15 V MIN TYP MAX 13 11 13 11 56 53 65 57 53 65 19 19 19 75 18 4 0.01 0.003 3.1 3.6 2.7 62 61 62 deg MHz 30 nV/Hz V pA/Hz % % ns 18 V/s 20 UNIT
f = 1 kHz RS = 1 k, f = 1 kHz
Full range is -40C to 85C. For VCC = 5 V, VI(PP) = 1 V; for VCC = 15 V, VI(PP) = 5 V. This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. For VCC = 5 V, VO(RMS) = 1 V; for VCC = 15 V, VO(RMS) = 6 V.
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TL052C and TL052AC electrical characteristics at specified free-air temperature
TL052C, TL052AC PARAMETER TEST CONDITIONS TA 25C Full range 25C Full range 25C to 70C 25C to 70C 25C 25C 70C 25C 70C 25C VICR Common-mode input voltage range Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C AVD ri ci CMRR Large-signal diff L i l differential ti l voltage am lification amplification Input resistance Input capacitance Common mode Common-mode rejection ratio VIC = VICRmin, min VO = 0, RS = 50 RL = 2 k 0C 70C 25C 25C 25C 0C 70C 65 65 65 -1 to 4 -1 to 4 3 3 2.5 2.5 -2.5 -2.5 -2.3 -2.3 25 30 20 59 65 46 1012 10 85 84 84 75 75 75 -3.2 -3.5 3.8 4.2 8 8 0.04 4 0.02 20 0.15 -2.3 to 5.6 100 1 200 4 -11 to 11 -11 to 11 13 13 11.5 11.5 -12 -12 -11 -11 50 60 30 105 129 85 1012 12 93 92 91 dB pF V/mV -12 -13.2 V 12.7 13.9 V 0.51 VCC = 5 V MIN TYP MAX 0.73 3.5 4.5 2.8 3.8 8 V/C 6 0.04 5 0.025 30 0.2 -12.3 to 15.6 100 1 200 4 25 V/mo pA nA pA nA 0.4 VCC = 15 V MIN TYP MAX 0.65 1.5 2.5 0.8 1.8 mV UNIT
TL052C VIO Input offset voltage VO = 0, 0 VIC = 0 0, RS = 50 TL052AC TL052C TL052AC VO = 0, RS = 50 VO = 0, , See Figure 5 VO = 0, , See Figure 5 VIC = 0, VIC = 0 0, VIC = 0 0,
aV
IO
Temperature coefficient of input offset voltage
Input offset-voltage long-term drift IIO IIB Input offset current Input bias current
V
VOM OM+
Maximum positive peak output voltage swing
RL = 10 k RL = 2 k RL = 10 k RL = 2 k
VOM OM-
Maximum negative peak g output voltage swing
Full range is 0C to 70C. This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150C, extrapolated to TA = 25C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. For VCC = 5 V, VO = 2.3 V; at VCC = 15 V, VO = 10 V.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
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TL052C and TL052AC electrical characteristics at specified free-air temperature (continued)
TL052C, TL052AC PARAMETER TEST CONDITIONS TA 25C kSVR Supply-voltage rejection S l lt j ti ratio (VCC/VIO) VO = 0, RS = 50 0C 70C 25C ICC VO1/VO2 S l t Supply current am lifiers) (two amplifiers) Crosstalk attenuation VO = 0, AVD = 100 No load 0C 70C 25C VCC = 5 V MIN TYP MAX 75 75 75 99 98 97 4.6 4.7 4.4 120 5.6 6.4 6.4 VCC = 15 V MIN TYP MAX 75 75 75 99 98 97 4.8 4.8 4.6 120 5.6 6.4 6.4 dB mA dB UNIT
TL052C and TL052AC operating characteristics at specified free-air temperature
TL052C, TL052AC PARAMETER TEST CONDITIONS TA 25C RL = 2 k, See Figure 1 CL = 100 pF, Full range 25C Full range 25C tr Rise time VI(PP) = 10 mV, () RL = 2 k, k CL = 100 pF F, See Figures 1 and 2 g 0C 70C 25C 0C 70C 25C Overshoot factor f = 10 Hz RS = 20 , See Figure 3 f = 1 kHz f = 10 Hz to 10 kHz 0C 70C Vn Equivalent input noise q voltage 25C 25C 25C 25C RL = 2 k, 25C 25C B1 Unity-gain bandwidth VI = 10 mV, V F, CL = 25 pF VI = 10 mV, mV F, CL = 25 pF, RL = 2 k, k See Figure 4 0C 70C 25C m Phase margin at unity gain RL = 2 k, k See Figure 4 0C 70C tf Fall time 55 54 63 55 54 62 24 24 24 71 19 4 0.01 0.003 3 3.2 2.6 60 59 60 15.4 VCC = 5 V MIN TYP MAX 17.8 VCC = 15 V MIN TYP MAX 9 8 9 8 56 55 63 57 56 64 19 19 19 71 19 4 0.01 0.003 3 3.2 2.7 63 63 63 deg MHz 30 nV/Hz V pA/Hz % % ns 17.8 20.7 V/s UNIT
SR+ SR- SR
Slew rate at unity gain Negative slew rate g at unity gain
Peak-to-peak equivalent VN(PP) input noise current In THD Equivalent input noise current Total harmonic distortion
f = 1 kHz RS = 1 k, f = 1 kHz
Full range is 0C to 70C. For VCC = 5 V, VI(PP) = 1 V; for VCC = 15 V, VI(PP) = 5 V. This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. For VCC = 5 V, VO(RMS) = 1 V; for VCC = 15 V, VO(RMS) = 6 V.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL052I and TL052AI electrical characteristics at specified free-air temperature
TL052I, TL052AI PARAMETER TEST CONDITIONS TA 25C Full range 25C Full range 25C to 85C 25C to 85C 25C 25C 85C VIC = 0, , 25C 85C 25C VICR Common-mode input voltage range Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C AVD ri ci CMRR Large-signal diff L i l differential ti l voltage am lification amplification Input resistance Input capacitance Common-mode Common mode rejection ratio VIC = VICRmin, min RS = 50 VO = 0, RL = 2 k -40C 85C 25C 25C 25C -40C 85C 65 65 65 -1 to 4 -1 to 4 3 3 2.5 2.5 -2.5 -2.5 -2.3 -2.3 25 30 20 59 74 43 1012 10 85 83 84 75 75 75 -3.2 -3.5 3.8 4.2 7 6 0.04 4 0.06 20 0.6 -2.3 to 5.6 100 10 200 20 -11 to 11 -11 to 11 13 13 11.5 11.5 -12 -12 -11 -11 50 60 30 105 145 76 1012 12 93 90 93 dB V/mV pF -12 -13.2 V 12.7 13.9 V 0.51 VCC = 5 V MIN TYP MAX 0.73 3.5 5.3 2.8 4.6 6 V/C 6 0.04 5 0.07 30 0.7 -12.3 to 15.6 100 10 200 20 25 V/mo pA nA pA nA 0.4 VCC = 15 V MIN TYP MAX 0.65 1.5 3.3 0.8 2.6 mV UNIT
TL052I VIO Input offset voltage VO = 0, 0 VIC = 0, RS = 50 TL052AI TL052I TL052AI Input offset-voltage long-term drift IIO IIB Input offset current Input bias current VO = 0, RS = 50 VO = 0, , See Figure 5 VO = 0, , See Figure 5 VIC = 0, VIC = 0, ,
aV
IO
Temperature coefficient T t ffi i t
V
VOM OM+
Maximum positive peak output voltage swing
RL = 10 k RL = 2 k RL = 10 k RL = 2 k
VOM OM-
Maximum negative peak g output voltage swing
Full range is -40C to 85C. This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150C, extrapolated to TA = 25C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. At VCC = 5 V, VO = 2.3 V; at VCC = 15 V, VO = 10 V.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL052I and TL052AI electrical characteristics at specified free-air temperature (continued)
TL052I, TL052AI PARAMETER TEST CONDITIONS TA 25C kSVR Supply-voltage rejection S l lt j ti ratio (VCC/VIO) VO = 0, RS = 50 -40C 85C 25C ICC VO1/VO2 S l t Supply current am lifiers) (two amplifiers) Crosstalk attenuation VO = 0, AVD = 100 No load -40C 85C 25C VCC = 5 V MIN TYP MAX 75 75 75 99 98 99 4.6 4.5 4.4 120 5.6 6.4 6.4 VCC = 15 V MIN TYP MAX 75 75 75 99 98 99 4.8 4.7 4.6 120 5.6 6.4 6.4 dB mA dB UNIT
TL052I and TL052AI operating characteristics at specified free-air temperature
TL052I, TL052AI PARAMETER TEST CONDITIONS TA 25C RL = 2 k, , See Figure 1 CL = 100 pF, , Full range 25C Full range 25C tr Rise time -40C 85C tf Fall time VI(PP) = 10 mV, RL = 2 k, CL = 100 pF, See Figures 1 and 2 25C -40C 85C 25C Overshoot factor f = 10 Hz RS = 20 , See Figure 3 f = 1 kHz f = 10 Hz to 10 kHz -40C 85C Vn Equivalent input noise q voltage 25C 25C 25C 25C RL = 2 k, 25C 25C B1 Unity-gain bandwidth VI = 10 mV, V F, CL = 25 pF VI = 10 mV, mV F, CL = 25 pF, RL = 2 k, k See Figure 4 -40C 85C 25C m Phase margin at unity gain RL = 2 k, k See Figure 4 -40C 85C 55 52 64 55 51 64 24% 24% 24% 71 19 4 0.01 0.003 3 3.5 2.5 60 58 60 15.4 VCC = 5 V MIN TYP MAX 17.8 VCC = 15 V MIN TYP MAX 9 8 9 8 56 53 65 57 53 65 19% 19% 19 71 19 4 0.01 0.003 3 3.6 2.6 63 61 63 deg MHz 30 nV/Hz V pA/Hz % % ns 17.8 20.7 V/s UNIT
SR+ SR- SR
Slew rate at unity gain Sl t t it i Negative slew rate at g unity gain
Peak-to-peak equivalent VN(PP) input noise current In THD Equivalent input noise current Total harmonic distortion
f = 1 kHz RS = 1 k, f = 1 kHz
Full range is -40C to 85C. For VCC = 5 V, VI(PP) = 1 V; for VCC = 15 V, VI(PP) = 5 V. This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. For VCC = 5 V, VO(RMS) = 1 V; for VCC = 15 V, VO(RMS) = 6 V.
12
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL054C and TL054AC electrical characteristics at specified free-air temperature
TL054C, TL054AC PARAMETER TEST CONDITIONS TA 25C Full range 25C Full range 25C to 70C 25C to 70C 25C VO = 0, VIC = 0, See Figure 5 VO = 0, VIC = 0, See Figure 5 25C 70C 25C 70C 25C VICR Common-mode input voltage range Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C AVD ri ci CMRR Large-signal differential L i l diff ti l voltage am lification amplification Input resistance Input capacitance Common-mode Common mode rejection ratio Supply-voltage Supply voltage rejection ratio (VCC/VIO) Supply current am lifiers) (four amplifiers) VIC = VICRmin, min VO = 0 0, RS = 50 VCC = 5 V to 15 V, V 0, VO = 0 RS = 50 RL = 2 k 0C 70C 25C 25C 25C 0C 70C 25C 0C 70C 25C ICC VO = 0, No load 0C 70C 65 65 65 75 75 75 -1 to 4 -1 to 4 3 3 2.5 2.5 -2.5 -2.5 -2.3 -2.3 25 30 20 72 88 57 1012 10 84 84 84 99 99 99 8.1 8.2 7.9 11.2 12.8 11.2 75 75 75 75 75 75 -3.2 -3.5 3.8 4.2 25 24 0.04 4 0.02 20 0.15 -2.3 to 5.6 100 1 200 4 -11 to 11 -11 to 11 13 13 11.5 11.5 -12 -12 -11 -11 50 60 30 133 173 85 1012 12 92 92 93 99 99 99 8.4 8.5 8.2 11.2 12.8 11.2 mA dB dB V/mV pF -12 -13.2 V 12.7 13.9 V 0.57 VCC = 5 V MIN TYP MAX 0.64 5.5 7.7 3.5 5.7 23 V/C 23 0.04 5 0.025 30 0.2 -12.3 to 15.6 100 1 200 4 V/mo pA nA pA nA 0.5 VCC = 15 V MIN TYP MAX 0.56 4 6.2 1.5 3.7 mV UNIT
TL054C VIO Input offset voltage TL054AC VO = 0 0, VIC = 0, RS = 50 TL054C TL054AC
aV
IO
Temperature coefficient of input offset voltage Input offset-voltage long-term drift
IIO IIB
Input offset current Input bias current
V
VOM OM+
Maximum positive peak output voltage swing
RL = 10 k RL = 2 k RL = 10 k RL = 2 k
VOM OM-
Maximum negative peak g output voltage swing
kSVR
VO1/VO2 Crosstalk attenuation AVD = 100 25C 120 120 dB Full range is 0C to 70C. Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150C, extrapolated to TA = 25C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. For VCC = 5 V, VO = 2.3 V, at VCC = 15 V, VO = 10 V.B
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13
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL054C and TL054AC operating characteristics at specified free-air temperature
TL054C, TL054C PARAMETER Positive slew rate at unity gain RL = 2 k, CL = 100 pF, See Figure 1 and Note 7 TEST CONDITIONS TA 25C 0C 70C 25C 0C 70C 25C tr Rise time VI(PP) = 10 mV, RL = 2 k, k CL = 100 pF F, See Figures 1 and 2 0C 70C 25C 0C 70C 25C Overshoot factor Equivalent input noise q voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current Total harmonic distortion Unity-gain bandwidth f = 10 Hz RS = 20 , See Figure 3 f = 1 kHz f = 10 Hz to 10 kHz 0C 70C Vn VN(PP) In THD 25C 25C 25C 25C RL = 2 k, 25C 25C B1 VI = 10 mV, mV CL = 25 pF F, VI = 10 mV, mV F, CL = 25 pF RL = 2 k, k See Figure 4 RL = 2 k k, See Figure 4 0C 70C 25C 0C 70C VCC = 5 V MIN TYP MAX 15.4 15.7 14.4 13.9 14.3 13.3 55 54 63 55 54 62 24% 24% 24% 75 21 4 0.01 0.003 2.7 3 2.4 61 60 61 VCC = 15 V MIN TYP MAX 10 8 8 10 8 8 17.8 17.9 17.5 15.9 16.1 15.5 56 55 63 57 56 64 19% 19% 19 75 21 4 0.01 0.003 2.7 3 2.4 64 64 63 deg MHz 45 nV/Hz V pA/Hz % % ns V/s UNIT
SR+
SR- SR
Negative slew rate at g unity gain
tf
Fall time
f = 1 kHz RS = 1 k, f = 1 kHz
m
Phase margin at unity gain
Full range is 0C to 70C. For VCC = 5 V, VI(PP) = 1 V; for VCC = 15 V, VI(PP) = 5 V. This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. For VCC = 5 V, VO(RMS) = 1 V; for VCC = 15 V, VO(RMS) = 6 V.
14
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL054I and TL054AI electrical characteristics at specified free-air temperature
TL054I, TL054AI PARAMETER TEST CONDITIONS TA 25C Full range 25C Full range 25C to 85C 25C to 85C 25C VO = 0, VIC = 0, See Figure 5 VO = 0, VIC = 0, See Figure 5 25C 85C 25C 85C 25C VICR Common-mode input voltage range Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C AVD ri ci CMRR Large-signal differential L i l diff ti l voltage am lification amplification Input resistance Input capacitance Common mode Common-mode rejection ratio Supply-voltage Supply voltage rejection ratio (VCC/VIO) Supply current am lifiers) (four amplifiers) VIC = VICRmin, min 0, VO = 0 RS = 50 VCC = 5 V to 15 V, V VO = 0 0, RS = 50 RL = 2 k -40C 85C 25C 25C 25C -40C 85C 25C -40C 85C 25C ICC VO = 0, No load -40C 85C 65 65 65 75 75 75 -1 to 4 -1 to 4 3 3 2.5 2.5 -2.5 -2.5 -2.3 -2.3 25 30 20 72 101 50 12 10 10 84 83 84 99 98 99 8.1 7.9 7.6 11.2 12.8 11.2 75 75 75 75 75 75 -3.2 -3.5 3.8 4.2 25 25 0.04 4 0.06 20 0.6 -2.3 to 5.6 100 10 200 20 -11 to 11 -11 to 11 13 13 11.5 11.5 -12 -12 -11 -11 50 60 30 133 212 70 12 10 12 92 92 93 99 99 99 8.4 8.2 7.9 11.2 12.8 11.2 mA dB dB V/mV pF -12 -13.2 V 12.7 13.9 V 0.57 VCC = 5 V MIN TYP MAX 0.64 5.5 8.8 3.5 6.8 24 V/C 23 0.04 5 0.07 30 0.7 -12.3 to 15.6 100 10 200 20 V/mo pA nA pA nA 0.5 VCC = 15 V MIN TYP MAX 0.56 4 7.3 1.5 4.8 mV UNIT
TL054I VIO In ut Input offset voltage TL054AI VO = 0 0, VIC = 0, RS = 50 TL054I TL054AI
aV
IO
Temperature coefficient of input offset voltage Input offset voltage long-term drift
IIO IIB
Input offset current Input bias current
V
VOM OM+
Maximum positive peak output voltage swing
RL = 10 k RL = 2 k RL = 10 k RL = 2 k
VOM OM-
Maximum negative peak g output voltage swing
kSVR
VO1/VO2 Crosstalk attenuation AVD = 100 25C 120 120 dB Full range is -40C to 85C. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150C, extrapolated to TA = 25C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. For VCC = 5 V, VO = 2.3 V, at VCC = 15 V, VO = 10 V.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TL054I and TL054AI operating characteristics at specified free-air temperature
TL054I, TL054AI PARAMETER Positive slew rate at unity gain RL = 2 k, See Figure 1 CL = 100 pF, TEST CONDITIONS TA 25C -40C 85C 25C -40C 85C 25C tr Rise time VI(PP) = 10 mV, RL = 2 k, CL = 100 pF, See Figures 1 and 2 -40C 85C 25C -40C 85C 25C Overshoot factor Equivalent input noise q voltage Peak-to-peak equivalent input noise voltage Equivalent input noise current Total harmonic distortion f = 10 Hz RS = 20 , See Figure 3 f = 1 kHz f = 10 Hz to 10 kHz -40C 85C Vn VN(PP) In THD 25C 25C 25C 25C RL = 2 k, 25C 25C B1 Unity-gain bandwidth VI = 10 mV, mV F, CL = 25 pF VI = 10 mV, mV CL = 25 pF F, k RL = 2 k, See Figure 4 RL = 2 k k, See Figure 4 -40C 85C 25C -40C 85C tf Fall time VCC = 5 V MIN TYP MAX 15.4 16.4 14 13.9 14.7 13 55 52 64 55 51 64 24 24 24 75 21 4 0.01 0.003% 2.7 3.3 2.3 61 59 61 VCC = 15 V MIN TYP MAX 10 8 8 10 8 8 17.8 18 17.3 15.9 16.1 15.3 56 53 65 57 53 65 19 19 19 75 21 4 0.01 0.003% 2.7 3.3 2.4 64 62 64 deg MHz 45 nV/Hz V pA/Hz % % ns V/s UNIT
SR+
SR- SR
Negative slew rate at g unity gain
f = 1 kHz RS = 1 k, f = 1 kHz
m
Phase margin at unity gain
Full range is -40C to 85C. For VCC = 5 V, VI(PP) = 1 V; for VCC = 15 V, VI(PP) = 5 V. This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. For VCC = 5 V, VO(RMS) = 1 V; for VCC = 15 V, VO(RMS) = 6 V.
16
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
VCC+ Overshoot VO 90% + VCC- CL (see Note A) 2 k VCC+ VI VO + - 100 VCC- RS RS - VI RL 10% NOTE A: CL includes fixture capacitance. tr
Figure 1. Slew Rate, Rise/Fall Time, and Overshoot Test Circuit
Figure 2. Rise-Time and Overshoot Waveform
10 k VCC+ + VCC- CL (see Note A) RL pA pA + - - VO
NOTE A: CL includes fixture capacitance.
Figure 3. Noise-Voltage Test Circuit
Figure 4. Unity-Gain Bandwidth and Phase-Margin Test Circuit
VCC+
typical values
Typical values, as presented in this data sheet represent the median (50% point) of device parametric performance.
Ground Shield
VCC-
input bias and offset current
At the picoamp-bias-current level typical of the TL05x and TL05xA, accurate measurement of the Figure 5. Input-Bias and Offset-Current Test Circuit bias current becomes difficult. Not only does this measurement require a picoammeter, but test-socket leakages easily can exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters with bias voltages applied, but with no device in the socket. The device then is inserted in the socket, and a second test that measures both the socket leakage and the device input bias current is performed. The two measurements then are subtracted algebraically to determine the bias current of the device.
noise
Because of the increasing emphasis on low noise levels in many of today's applications, the input noise voltage density is sample tested at f = 1 kHz. Texas Instruments also has additional noise-testing capability to meet specific application requirements. Please contact the factory for details.
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE VIO Input offset voltage Temperature coefficient of input offset voltage Input bias current Input offset current Common-mode input voltage range limits Output voltage Maximum peak output voltage Maximum peak-to-peak output voltage Large-signal differential voltage amplification Distribution Distribution vs Common-mode input voltage vs Free-air temperature vs Free-air temperature vs Supply voltage vs Free-air temperature vs Differential input voltage vs Supply voltage vs Output current vs Free-air temperature vs Frequency vs Load resistance vs Frequency vs Free-air temperature vs Frequency vs Free-air temperature vs Frequency vs Free-air temperature vs Supply voltage vs Time vs Free-air temperature vs Supply voltage vs Free-air temperature vs Load resistance vs Free-air temperature vs Load capacitance vs Frequency vs Frequency vs Supply voltage vs Free-air temperature vs Supply voltage vs Load capacitance vs Free-air temperature vs Frequency vs Time vs Time 6-11 12, 13, 14 15 16 16 17 18 19, 20 21 25, 26 27, 28 22, 23, 24 29 30 31, 32, 33 34, 35 36 37 38 39 40 41 42, 43, 44 45, 46, 47 48-53 54-59 60 61, 62 63 64, 65, 66 67, 68, 69 70, 71, 72 73, 74, 75 76, 77, 78 30 79 80
aV
IIB IIO
IO
VIC VO VOM VO(PP) AVD CMRR zo kSVR IOS ICC SR
Common-mode rejection ratio Output impedance Supply-voltage rejection ratio Short-circuit output current
Supply current Slew rate Overshoot factor
Vn THD B1 m
Equivalent input noise voltage Total harmonic distortion Unity-gain bandwidth
Phase margin Phase shift Voltage-follower small-signal pulse response Voltage-follower large-signal pulse response
18
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TL051 INPUT OFFSET VOLTAGE
16 433 Units Tested From 1 Wafer Lot VCC = 15 V TA = 25C P Package 20
DISTRIBUTION OF TL051A INPUT OFFSET VOLTAGE
16 Percentage of Units - %
Percentage of Units - %
12
12
8
8
4
4
0 -1.5 -1.1 -0.9 -0.6 -0.3
0
0.3
0.6
0.9 1.1 1.5
0 -900
VIO - Input Offset Voltage - mV
Figure 6
DISTRIBUTION OF TL052 INPUT OFFSET VOLTAGE
15 476 Amplifiers Tested From 1 Wafer Lot VCC = 15 V TA = 25C P Package 20
Percentage of Amplifiers - %
Percentage of Amplifiers - %
12
15
9
10
6
5
3
0 -1.5 -1.2 -0.9 -0.6 -0.3
0
0.3
0.6
0.9
1.2 1.5
0 -900
VIO - Input Offset Voltage - mV
Figure 8
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IIIIIIIIII IIIIIIIIII IIIIIIIIII
393 Units Tested From 1 Wafer Lot VCC = 15 V TA = 25C P Package -600 -300 0 300 600 900 VIO - Input Offset Voltage - V
Figure 7
DISTRIBUTION OF TL052A INPUT OFFSET VOLTAGE
403 Amplifiers Tested From 1 Wafer Lot VCC = 15 V TA = 25C P Package
-600
-300
0
300
600
900
VIO - Input Offset Voltage - V
Figure 9
19
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TL054 INPUT OFFSET VOLTAGE
30 1140 Amplifiers Tested From 3 Wafer Lots VCC = 15 V TA = 25C N Package 15 1048 Amplifiers Tested From 3 Wafer Lots VCC = 15 V TA = 25C N Package
DISTRIBUTION OF TL054A INPUT OFFSET VOLTAGE
25 Percentage of Amplifiers - %
20
Percentage of Amplifiers - % 4
12
9
15
6
10
5
3
0 -4
-3
-2
-1
0
1
2
3
0 -1.8
-1.2
-0.6
0
0.6
1.2
1.8
VIO - Input Offset Voltage - mV
VIO - Input Offset Voltage - mV
Figure 10
DISTRIBUTION OF TL051 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT
20 20
Figure 11
DISTRIBUTION OF TL052 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT
Percentage of Amplifiers - %
16 Percentage of Units - %
12
8
4
0 -25 -20 -15 -10 -5
20
IIIIIIIIII
0 5 10 15 20 25
120 Units Tested From 2 Wafer Lots VCC = 15 V TA = 25C to 125C P Package
15
10
aV
IO
- Temperature Coefficient - V/C
Figure 12
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IIIIIIIIII IIIIIIIIIII IIIIIIIIIII
172 Amplifiers Tested From 2 Wafer Lots VCC = 15 V TA = 25C to 125C P Package Outlier: One Unit at -34.6 V/C 5 0 -30
a V - Temperature Coefficient - V/C
IO
-20
-10
0
10
20
30
Figure 13
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TL054 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE
10 VCC = 15 V TA = 25C IB - Input Bias Current - nA I 5
Percentage of Amplifiers - %
40
30
20
10
0 -60
IB and IO - Input Bias and Offset Currents - nA
100
10 IIB 1 IIO 0.1
VIC - Common-Mode Input Voltage - V
VCC = 15 V VO = 0 VIC = 0
4 0 -4 -8 -12 -16
0.01
0.001 25 45 65 85 105 TA - Free-Air Temperature - C 125
0
2
4 6 8 10 12 |VCC| - Supply Voltage - V
Figure 16
Figure 17
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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IIIII
IIIII
IIIIIIIIIIII IIIIIIIIIIII
324 Amplifiers Tested From 3 Wafer Lots VCC = 15 V TA = 25C to 125C N Package -40 -20 0 20 40 60
50
0
-5
-10 -15
-10
-5
0
5
10
15
aV
IO
- Temperature Coefficient - V/C
VIC - Common-Mode Input Voltage - V
Figure 14
Figure 15
COMMON-MODE INPUT VOLTAGE RANGE LIMITS vs SUPPLY VOLTAGE
16 TA = 25C 12 8 Positive Limit
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE
Negative Limit
I I
14
16
21
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
COMMON-MODE INPUT VOLTAGE RANGE LIMITS vs FREE-AIR TEMPERATURE
20 VIC - Common-Mode Input Voltage - V 15 10 5 0 -5 -10 -15 -20 -75
OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE
5 4 3 VO - Output Voltage - V 2 1 0 -1 -2 -3 -4
VCC = 15 V
Positive Limit
-50
-25 0 25 50 75 100 TA - Free-Air Temperature - C
125
-5 -200
-100
0
VID - Differential Input Voltage - V
Figure 18
OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE
Figure 19
MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE
16 TA = 25C VOM - Maximum Peak Output Voltage - V 12 RL = 10 k 8 RL = 2 k 4 0 -4 RL = 2 k -8 RL = 10 k -12 VOM- -16 0 2 4 6 8 10 12 |VCC| - Supply Voltage - V 14 16 VOM+
10
VO - Output Voltage - V
5
0
-5
-10
-15 -400
-200
0
VID - Differential Input Voltage - V
Figure 20
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
IIII AAAA IIII IIII AAAA IIII IIII AAAA AAAA
IIII IIIII IIIII
15
VCC = 15 V TA = 25C
RL = 600 RL = 1 k RL = 2 k RL = 10 k
200
400
Figure 21
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IIIII IIIII IIIII
Negative Limit
IIII IIIII IIII IIII IIII IIII IIII
RL = 600 RL = 1 k RL = 2 k RL = 10 k 100 200
VCC = 5 V TA = 25C
IIIII IIIIIIIIII IIIII IIIII IIIII
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY
VO(PP) - Maximum Peak-to-Peak Output Voltage - V 30 VCC = 15 V 25 RL = 2 k
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY
VO(PP) - Maximum Peak-to-Peak Output Voltage - V
25
20
20
15 TA = 125C 10 VCC = 5 V TA = -55C
15
10
5
5
0 10 k 100 k 1M f - Frequency - Hz 10 M
0 10 k
Figure 22
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY
VO(PP) - Maximum Peak-to-Peak Output Voltage - V 30 |VOM| - Maximum Peak Output Voltage - V 5
25
RL = 10 k TA = 25C
VCC = 15 V
4
20
3
15
VOM+
10
VCC = 5 V
5
1
0 10 k
100 k
1M
10 M
0 0 2 4 6 8 10 12 14 16 18 20 |IO| - Output Current - mA
f - Frequency - Hz
Figure 24
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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AAA AAA
2
VOM-
Figure 25
AAAAA AAAAA AAAAA AAAAA
AAA AAA
AAAAA AAAAA AAAAA AAAAA
VCC = 5 V 100 k f - Frequency - Hz
VCC = 15 V
1M
Figure 23
MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT
VCC = 5 V RL = 10 k TA = 25C
AAAA AAAA AAAA
RL = 2 k TA = 25C 10 M 23
30
AAAAA AAAAA AAAA AAAA AAAAA AAAAA
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
5 VOM+ V OM - Maximum Peak Output Voltage - V 4 3 2 1 0 -1 -2 -3 -4 VCC = 5 V RL = 2 k RL = 10 k
|VOM| - Maximum Peak Output Voltage - V
14 12 10 8 6 4 2 0 0 5
10
15 20 25 30 35 40 |IO| - Output Current - mA
45
50
-5 -75
Figure 26
MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
16 V OM - Maximum Peak Output Voltage - V 12 8 4 0 -4 -8 -12 A VD - Differential Voltage Amplification - V/mV RL = 10 k 250
VOM+
RL = 2 k
200
VCC = 15 V
150 VCC = 5 V 100
VOM-
RL = 2 k RL = 10 k 125
50
-16 -75
-50
-25 0 25 50 75 100 TA - Free-Air Temperature - C
0 0.4
Figure 28
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
24
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AAA AAA
AAA AAA AAAA AAAA AAAAA AAAAA AAAAA AAAAA
VCC = 15 V RL = 10 k TA = 25C VOM+ VOM-
16
VOM-
RL = 2 k
RL = 10 k 125
-50
-25 0 25 50 75 100 TA - Free-Air Temperature - C
Figure 27
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs LOAD RESISTANCE
VO = 1 V TA = 25C VCC = 15 V
AAA AAA AAA AAA
1
4 10 RL - Load Resistance - k
40
100
Figure 29
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY
VCC = 15 V RL = 2 k CL = 25 pF TA = 25C AVD 103 102 101 60 90 Phase Shift 120 150 180 10 M
106 A VD - Differential Voltage Amplification - V/mV 105 104
0 30 m - Phase Shift
1 0.1 10 100 1k 10 k 100 k f - Frequency - Hz 1M
Figure 30
TL051 AND TL052 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE
1000 A VD - Differential Voltage Amplification - V/mV A VD - Differential Voltage Amplification - V/mV VCC = 5 V VO = 2.3 V 400 1000 VCC = 5 V VO = 2.3 V 400
TL054 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE
RL = 10 k 100
RL = 10 k 100 RL = 2 k 40
40
RL = 2 k
10 -75
-50
-25
0
25
50
75
100
125
10 -75
-50
-25
0
25
50
75
100
125
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 31
Figure 32
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
25
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE
1000 A VD - Differential Voltage Amplification - V/mV CMRR - Common-Mode Rejection Ratio - dB
COMMON-MODE REJECTION RATIO vs FREQUENCY
100 90 80 70 60 50 40 30 20 10 0 10 100 1k 10 k 100 k 1M 10 M VCC = 5 V TA = 25C
400
RL = 10 k
100
RL = 2 k
40
10 -75
-50
-25
0
25
TA - Free-Air Temperature - C
Figure 33
COMMON-MODE REJECTION RATIO vs FREQUENCY
100 CMRR - Common-Mode Rejection Ratio - dB 90 80 70 60 50 40 30 20 10 0 10 100 1k 10 k 100 k 1M f - Frequency - Hz 10 M VCC = 15 V TA = 25C CMRR - Common-Mode Rejection Ratio - dB 100
Figure 35
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
26
AAAAA AAAAA
50 75 100 125
POST OFFICE BOX 655303
VCC = 15 V VO = 10 V
f - Frequency - Hz
Figure 34
COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE
VIC = VICRMin 95 VCC = 15 V
90
85 VCC = 5 V 80
75
70 -75
-50
-25
0
25
50
75
100
125
TA - Free-Air Temperature - C
Figure 36
* DALLAS, TEXAS 75265
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE vs FREQUENCY
100 40 zo - Output Impedance - AVD = 100 kSVR k SVR - Supply-Voltage Rejection Ratio - dB 110 VCC = 5 V to 15 V 106
SUPPLY-VOLTAGE REJECTION RATIO vs FREE-AIR TEMPERATURE
10 AVD = 10 4
102
98
1 AVD = 1 0.4 VCC = 15 V TA = 25C ro (open loop) 250 1k 10 k 100 k f - Frequency - Hz 1M
94
0.1
Figure 37
SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE
60 IOS - Short-Circuit Output Current - mA I OS
40
IOS - Short-Circuit Output Current - mA I OS
VO = 0 TA = 25C VID = 100 mV
20
0
-20 VID = -100 mV -40
-60 0 2 6 8 10 12 |VCC| - Supply Voltage - V 4 14 16
Figure 39
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
AA AA AA AA AA AA
90 -75
-50
-25 0 25 50 75 100 TA - Free-Air Temperature - C
125
Figure 38
SHORT-CIRCUIT OUTPUT CURRENT vs TIME
60 VID = 100 mV 40
20
-20
-40 VID = -100 mV -60 VCC = 15 V TA = 25C 0 10 20 30 t - Time - s 40 50 60
AA AA
0
Figure 40
* DALLAS, TEXAS 75265
27
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT vs FREE-AIR TEMPERATURE
60 IOS - Short-Circuit Output Current - mA I OS VCC = 15 V 3
TL051 SUPPLY CURRENT vs SUPPLY VOLTAGE
VCC = 5 V
ICC I CC - Supply Current - mA
20
0 VCC = 5 V
VID = -100 m V
VCC = 15 V
-40
VO = 0 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C 125
-60 -75
Figure 41
TL052 SUPPLY CURRENT vs SUPPLY VOLTAGE
5 10
4 I CC - Supply Current - mA ICC ICC I CC - Supply Current - mA TA = 25C TA = -55C 3 TA = 125C
6
2
4
1 VO = 0 No Load 0 0 2 4 6 8 10 12 14 16 |VCC| - Supply Voltage - V
2 VO = 0 No Load 0 0 2 4 6 8 10 12 14 16 |VCC| - Supply Voltage - V
Figure 43
Figure 44
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
28
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIII IIIII
AA AA AA
AA AA
IIIIII
-20
IIIII IIIII
VID = 100 m V
40
2.5 TA = 25C TA = -55C TA = 125C 1.5
2
1
0.5 VO = 0 No Load 0 0 2 4 6 8 10 12 14 16 |VCC| - Supply Voltage - V
AA AA AA AA AA
Figure 42
TL054 SUPPLY CURRENT vs SUPPLY VOLTAGE
8 TA = 25C TA = -55C TA = 125C
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL051 SUPPLY CURRENT vs FREE-AIR TEMPERATURE
3 5
TL052 SUPPLY CURRENT vs FREE-AIR TEMPERATURE
2.5 ICC I CC - Supply Current - mA VCC = 15 V 2 VCC = 5 V ICC I CC - Supply Current - mA
4
VCC = 15 V VCC = 5 V
3
1.5
2
1
0.5 VO = 0 No Load 0 -75 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C 125
Figure 45
TL054 SUPPLY CURRENT vs FREE-AIR TEMPERATURE
10 25
VCC = 15 V VCC = 5 V
8 I CC - Supply Current - mA ICC
SR - Slew Rate - V/s
6
4
2 VO = 0 No Load 0 -75 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - C 125
Figure 47
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
AA AA AA
IIIIII IIIIII IIIIII IIIIII
AA AA AA AA AA
1 VO = 0 No Load 0 -75 -50 -25 0 25 50 75 100 125
TA - Free-Air Temperature - C
Figure 46
TL051 SLEW RATE vs LOAD RESISTANCE
SR+ 20 SR- 15
10
5
VCC = 5 V CL = 100 pF TA = 25C See Figure 1 1 4 10 40 100
0 0.4
RL - Load Resistance - k
Figure 48
* DALLAS, TEXAS 75265
29
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL052 SLEW RATE vs LOAD RESISTANCE
25 SR+ 20 SR - Slew Rate - V/s 20 25
TL054 SLEW RATE vs LOAD RESISTANCE
SR - Slew Rate - V/s
15
SR-
15
10
10
5
VCC = 5 V CL = 100 pF TA = 25C See Figure 1 0.4 1 4 10 40 100
5
0 RL - Load Resistance - k
0 0.4
1
4
RL - Load Resistance - k
Figure 49
TL051 SLEW RATE vs LOAD RESISTANCE
30 SR+ 25 SR- SR - Slew Rate - V/s SR - Slew Rate - V/s 20 20 25
Figure 50
TL052 SLEW RATE vs LOAD RESISTANCE
SR+
15
15
10
10 VCC = 15 V CL = 100 pF TA = 25C See Figure 1 1 4 10 40 100
5
5
0 0.4
0 0.4 1 4 10 RL - Load Resistance - k 40 100
RL - Load Resistance - k
Figure 51
Figure 52
30
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* DALLAS, TEXAS 75265
II
SR+ SR- VCC = 5 V CL = 100 pF TA = 25C See Figure 1 10 40 100 SR- VCC = 15 V CL = 100 pF TA = 25C See Figure 1
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL054 SLEW RATE vs LOAD RESISTANCE
25 SR+ 20 SR - Slew Rate - V/s SR - Slew Rate - V/s 30
TL051 SLEW RATE vs FREE-AIR TEMPERATURE
25 SR+ 20
SR- 15
15
SR-
10 VCC = 5 V CL = 100 pF TA = 25C See Figure 1 1 4 10 40 100
10 VCC = 5 V RL = 2 k
5
5
0 0.4
0 -75
-50
-25
0
25
50
75
100
125
RL - Load Resistance - k
TA - Free-Air Temperature - C
Figure 53
TL052 SLEW RATE vs FREE-AIR TEMPERATURE
25 20
Figure 54
TL054 SLEW RATE vs FREE-AIR TEMPERATURE
20 SR - Slew Rate - V/s
SR+ SR+ SR - Slew Rate - V/s 15 SR-
15
SR-
10
10 VCC = 5 V RL = 2 k CL = 100 pF See Figure 1 -50 -25 0 25 50 75 100 125
5
5
VCC = 5 V RL = 2 k CL = 100 pF See Figure 1 -50 -25 0 25 50 75 100 125
0 -75
0 -75
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 55
Figure 56
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
31
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL051 SLEW RATE vs FREE-AIR TEMPERATURE
30 SR+ 20 20 SR- 15 SR - Slew Rate - V/s SR - Slew Rate - V/s SR- 15 25 SR+
TL052 SLEW RATE vs FREE-AIR TEMPERATURE
25
10 VCC = 15 V RL = 2 k CL = 100 pF See Figure 1 -50 -25 0 25 50 75 100 125
10 VCC = 15 V RL = 2 k CL = 100 pF See Figure 1 -50 -25 0 25 50 75 100 125
5
5
0 -75
0 -75
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 57
TL054 SLEW RATE vs FREE-AIR TEMPERATURE
20 SR+ SR- SR - Slew Rate - V/s Overshoot Factor - % 15 40 50
Figure 58
OVERSHOOT FACTOR vs LOAD CAPACITANCE
30
10
20
5
0 -75
VCC = 15 V RL = 2 k CL = 100 pF See Figure 1 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C
10
0 0 50
CL - Load Capacitance - pF
Figure 59
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
32
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIIII IIIII IIIII IIIII IIIII IIIII IIIII IIII IIII
VCC = 5 V VCC = 15 V VI(PP) = 10 mV RL = 2 k TA = 25C See Figure 1 100 150 200 250
300
Figure 60
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL051 EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
Vn - Equivalent Input Noise Voltage - nV/ Hz Vn - Equivalent Input Noise Voltage - nV/ Hz 100 VCC = 15 V RS = 20 TA = 25C See Figure 3 100
TL052 AND TL054 EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
70
70
50 40 30
50 40 30
20
20
10 10 100 1k 10 k f - Frequency - Hz
10 100 k 10 100 1k f - Frequency - Hz 10 k
Figure 61
TOTAL HARMONIC DISTORTION vs FREQUENCY
1 0.4 VCC = 15 V AVD = 1 VO(RMS) = 6 V TA = 25C 3.2
Figure 62
TL051 UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE
THD - Total Harmonic Distortion - %
B1 - Unity-Gain Bandwidth - MHz
3.1
0.1 0.04
3
2.9 VI = 10 mV RL = 2 k CL = 25 pF TA = 25C See Figure 4 0 2 4 6 8 10 12 14 16
0.01 0.004
2.8
0.001 100 1k 10 k 100 k f - Frequency - Hz
2.7 |VCC| - Supply Voltage - V
Figure 63
Figure 64
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
AAAAA AAAAA AAAAA AAAAA
VCC = 15 V RS = 20 TA = 25C See Figure 3 100 k 33
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL052 UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE
3.2 2.9
TL054 UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE
B1 - Unity-Gain Bandwidth - MHz
B1 - Unity-Gain Bandwidth - MHz
3.1
2.8
3
2.7
2.8
VI = 10 mV RL = 2 k CL = 25 pF TA = 25C See Figure 4
2.5
2.7 4 6 8 10
2.4 0 2 4 6 8
12
14
16
10
|VCC| - Supply Voltage - V
|VCC| - Supply Voltage - V
Figure 65
TL051 UNITY-GAIN BANDWIDTH vs FREE-AIR TEMPERATURE
4 VCC = 15 V B1 - Unity-Gain Bandwidth - MHz B1 - Unity-Gain Bandwidth - MHz 3 VCC = 5 V 2 3 4
Figure 66
TL052 UNITY-GAIN BANDWIDTH vs FREE-AIR TEMPERATURE
2 VCC = 5 V to 15 V VI = 10 mV RL = 2 k CL = 25 pF TA = 25C See Figure 4
1
VI = 10 mV RL = 2 k CL = 25 pF See Figure 4
1
0 -75
-50
-25
0
25
50
75
100
125
0 -75
-50
-25
0
25
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 67
Figure 68
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
34
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIAIIII I IIAAAAA IAAAI IIIA IIIII IAAAAA IIIII IIIII IIIII IIIII AAAAA IIII AAAAA IIII
VI = 10 mV RL = 2 k CL = 25 pF TA = 25C See Figure 4 12 14 16 50 75 100 125
AAAA AAAA AAAA AAAA AAAA
2.9
2.6
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL054 UNITY-GAIN BANDWIDTH vs FREE-AIR TEMPERATURE
4 65
TL051 PHASE MARGIN vs SUPPLY VOLTAGE
B1 - Unity-Gain Bandwidth - MHz
63 3 m - Phase Margin 61
2 VCC = 5 V to 15 V VI = 10 mV RL = 2 k CL = 25 pF TA = 25C See Figure 4
59 VI = 10 mV RL = 2 k CL = 25 pF TA = 25C See Figure 4 0 2 4 6 8 10 12 14 16
1
57
0 -75
55 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C |VCC| - Supply Voltage - V
Figure 69
TL052 PHASE MARGIN vs SUPPLY VOLTAGE
65 65
Figure 70
TL054 PHASE MARGIN vs SUPPLY VOLTAGE
63 m - Phase Margin m - Phase Margin
63
61
61
59 VI = 10 mV RL = 2 k CL = 25 pF TA = 25C See Figure 4 4 6 8 10 12 14 16
59
57
57
55 |VCC| - Supply Voltage - V
55 0 2 4 6 8
10
|VCC| - Supply Voltage - V
Figure 71
Figure 72
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
AAAAA AAAAA AAAAA AAAAA AAAAA
VI = 10 mV RL = 2 k CL = 25 pF TA = 25C See Figure 4 12 14 16 35
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL051 PHASE MARGIN vs LOAD CAPACITANCE
70 VI = 10 mV RL = 2 k TA = 25C See Figure 4 m - Phase Margin 70 VI = 10 mV RL = 2 k TA = 25C See Figure 4
TL052 PHASE MARGIN vs LOAD CAPACITANCE
65
65
m - Phase Margin
60 VCC = 15 V See Note A 55 VCC = 5 V 50
See Note A
55
45
50
40 0 10 20 30 40 50 60 70 80 CL - Load Capacitance - pF 90 100
45
0
10
Figure 73
TL054 PHASE MARGIN vs LOAD CAPACITANCE
70 VI = 10 mV RL = 2 k TA = 25C See Figure 4
65
m - Phase Margin
60 See Note A VCC = 5 V
VCC = 15 V
50
45
0
10
Values of phase margin below a load capacitance of 25 pF were estimated.
36
POST OFFICE BOX 655303
IIIII
55
20 30 40 50 60 70 80 CL - Load Capacitance - pF
Figure 75
* DALLAS, TEXAS 75265
IIIII IIIII IIIII
VCC = 5 V 20 30 40 50 60 70 80 CL - Load Capacitance - pF 90 100
60
VCC = 15 V
Figure 74
IIIII IIIII
90 100
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL051 PHASE MARGIN vs FREE-AIR TEMPERATURE TL052 PHASE MARGIN vs FREE-AIR TEMPERATURE
63
VI = 10 mV RL = 2 k CL = 25 pF See Figure 4
VCC = 15 V m - Phase Margin
63
m - Phase Margin
61
61
VCC = 5 V 59
59 VCC = 5 V 57
57
55 -75
-50
-25 0 25 50 75 100 TA - Free-Air Temperature - C
125
55
-75
Figure 76
TL054 PHASE MARGIN vs FREE-AIR TEMPERATURE
65
63
VCC = 15 V
m- Phase Margin
61
59 VCC = 5 V 57
55
-75
-50
-25 0 25 50 75 100 TA - Free-Air Temperature - C
Figure 78
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
AAAAA AAAAA AAAAA AAAAA
VI = 10 mV RL = 2 k CL = 25 pF See Figure 4 -50
AAAAA AAAAA AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA
65
65
VCC = 15 V
-25 0 25 50 75 100 TA - Free-Air Temperature - C
125
Figure 77
VI = 10 mV RL = 2 k CL = 25 pF See Figure 4
125
37
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE
16 12 VO - Output Voltage - mV 8 VO - Output Voltage - V 4 0 -4 -8 -12 -16 0 0.2 0.4 0.6 0.8 1.0 1.2 t - Time - s 8 6 4 2 0 -2 -4 -6 -8 0 1 2 3 4 5 6 t - Time - s
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE
VCC = 15 V RL = 2 k CL = 100 pF TA = 25C See Figure 1
Figure 79
Figure 80
38
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
AAAAA AAAAA AAAAA AAAAA AAAAA
VCC = 15 V RL = 2 k CL = 100 pF TA = 25C See Figure 1
AAAAA AAAAA AAAAA AAAAA
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION output characteristics
All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance. The TL05x and TL05xA drive higher capacitive loads; however, as the load capacitance increases, the resulting response pole occurs at lower frequencies, causing ringing, peaking, or even oscillation. The value of the load capacitance at which oscillation occurs varies with production lots. If an application appears to be sensitive to oscillation due to load capacitance, adding a small resistance in series with the load should alleviate the problem. Capacitive loads of 1000 pF, and larger, may be driven if enough resistance is added in series with the output (see Figure 81 and Figure 82).
(a) CL = 100 pF, R = 0
(b) CL = 300 pF, R = 0
(c) CL = 350 pF, R = 0
(d) CL = 1000 pF, R = 0
(e) CL = 1000 pF, R = 50
(f) CL = 1000 pF, R = 2 k
Figure 81. Effect of Capacitive Loads
15 V - -5 V -15 V CL (see Note A) 2 k NOTE A: CL includes fixture capacitance.
POST OFFICE BOX 655303
R
Figure 82. Test Circuit for Output Characteristics
+
5V
VO
* DALLAS, TEXAS 75265
39
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION input characteristics
The TL05x and TL05xA are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Because of the extremely high input impedance and resulting low-bias current requirements, the TL05x and TL05xA are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets easily can exceed bias current requirements and cause degradation in system performance. It is good practice to include guard rings around inputs (see Figure 83). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input. Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
VI + - VO VI + (c) UNITY-GAIN AMPLIFIER - VO + (b) INVERTING AMPLIFIER - VO VI
(a) NONINVERTING AMPLIFIER
Figure 83. Use of Guard Rings
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input-bias current requirements of the TL05x and TL05xA result in a very low current noise. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 50 k.
40
POST OFFICE BOX 655303
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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION phase meter
The phase meter in Figure 84 produces an output voltage of 10 mV per degree of phase delay between the two input signals VA and VB. The reference signal VA must be the same frequency as VB. The TLC3702 comparators (U1) convert these two input sine waves into 5-V square waves. Then, R1 and R4 provide level shifting prior to the SN74HC109 dual J-K flip flops. Flip-flop U2B is connected as a toggle flip-flop and generates a square wave at one-half the frequency of VB. Flip-flop U2A also produces a square wave at one-half the input frequency. The pulse duration of U2A varies from zero to one-half the period, where zero corresponds to zero phase delay between VA and VB and one-half the period corresponds to VB lagging VA by 360 degrees. The output pulse from U2A causes the TLC4066 (U3) switch to charge the TL05x (U4) integrator capacitors C1 and C2. As the phase delay approaches 360 degrees, the output of U4A approximates a square wave, and U2A has an output of almost 2.5 V. U4B acts as a noninverting amplifier with a gain of 1.44 in order to scale the 0- to 2.5-V integrator output to a 0- to 3.6-V output range. R8 and R10 provide output gain and zero-level calibration. This circuit operates over a 100-Hz to 10-kHz frequency range.
+5 V
R2 100 k
+5 V
C2 0.016 F R6 R7 10 k C1 0.016 F + U4A - + U4B - R9 20 k
VA U1A
R1 100 k
S 1J U2A C1 1K R
U3 NC R5 10 k
10 k
VO
R3 100 k
S 2J C1 2K R
NC U2B Gain
R8 50 k +5 V R10 10 k Zero -5 V
R4 100 k VB U1B
NOTE A: U1 = TLC3702; VCC = 5 V U2 = SN74HC109 U3 = TLC4066 U4, U5 = TL05x; VCC = 5 V
Figure 84. Phase Meter
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
41
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION precision constant-current source over temperature
A precision current source (see Figure 85) benefits from the high input impedance and stability of Texas Instruments enhanced-JFET process. A low-current shunt regulator maintains 2.5 V between the inverting input and the output of the TL05x. The negative feedback then forces 2.5 V across the current-setting resistor R; therefore, the current to the load simply is 2.5 V divided by R. Possible choices for the shunt regulator include the LT1004, LT1009, and LM385. If the regulator's cathode connects to the operational amplifier output, this circuit sources load current. Similarly, if the cathode connects to the inverting input, the circuit sinks current from the load. To minimize output current change with temperature, R should be a metal film resistor with a low temperature coefficient. Also, this circuit must be operated with split-voltage supplies.
150 pF 150 pF
U2
U2
+15 V - U1 IO + -15 V R
POST OFFICE BOX 655303
+15 V 100 k - U1 II + -15 V Load V = 0 to -10 V R (b) SINK CURRENT LOAD
100 k
Load V = 0 to 10 V
(a) SOURCE CURRENT LOAD NOTE A: U1 = 1/2 TL05x U2 = LM385, LT1004, or LT1009 voltage reference I= 2.5 V , R = Low-temperature-coefficient metal-film resistor R
Figure 85. Precision Constant-Current Source
42
* DALLAS, TEXAS 75265
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION instrumentation amplifier with adjustable gain/null
The instrumentation amplifier in Figure 86 benefits greatly from the high input impedance and stable input offset voltage of the TL05xA. Amplifiers U1A, U1B, and U2A form the actual instrumentation amplifier, while U2B provides offset null. Potentiometer R1 provides gain adjustment. With R1 = 2 k, the circuit gain equals 100, while with R1 = 200 k, the circuit gain equals two. The following equation shows the instrumentation amplifier gain as a function of R1: R2 R3 1 AV R1
+)
)
Readjusting the offset null is necessary when the circuit gain is changed. If U2B is needed for another application, R7 can be terminated at ground. The low input offset voltage of the TL05xA minimizes the dc error of the circuit. For best matching, all resistors should be one-percent tolerance. The matching between R4, R5, R6, and R7 controls the CMRR of this application. The following equation shows the output voltages when the input voltage equals zero. This dc error can be nulled by adjusting the offset null potentiometer; however, any change in offset voltage over time or temperature also creates an error. To calculate the error from changes in offset, consider the three offset components in the equation as delta offsets, rather than initial offsets. The improved stability of Texas Instruments enhanced JFETs minimizes the error resulting from change in input offset voltage with time. Assuming VI equals zero, VO can be shown as a function of the offset voltage: V
O
+ VIO2 1 ) R3 R1
-V R3 IO1 R1
VI- + U1A -
) R7 1 ) R4 ) R1 R4 R7 1 ) R6 ) R6 1 ) R2 ) V 1 ) R6 IO3 R4 R4 R4 R5 ) R7 R1
R7 R6 R2 R6 R5
R4 10 k 100 k R2 R6 10 k
200 k 10 turn AV = 2 to 100 2 k R1
10 M 10 M R3 100 k U1B VI+ + R5 10 k
R7 10 k
U2B +
NOTE A: U1 and U2 = TL05xA; VCC = 15 V.
Figure 86. Instrumentation Amplifier
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
-
- U2A + VCC+ 82 k Offset Null 1 k 0.1 F 82 k VCC- 43 VO
-
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION high input impedance log amplifier
The low input offset voltage and high input impedance of the TL05xA creates a precision log amplifier (see Figure 87). IC1 is a 2.5-V, low-current precision, shunt regulator. Transistors Q1 and Q2 must be a closely matched npn pair. For best performance over temperature, R4 should be a metal-film resistor with a low temperature coefficient. In this circuit, U1A serves as a high-impedance unity-gain buffer. Amplifier U1B converts the input voltage to a current through R1 and Q1. Amplifier U1C, IC1, and R4 form a 1-A temperature-stable current source that sets the base-emitter voltage of Q2. U1D amplifies the difference between the base-emitter voltage of Q1 and Q2 (see Figure 88). The output voltage is given by the following equation: V
O
+ - 1 ) R6 R5
kT q
V In R1
Q1
I 10 -6
Q2
1
where k 1.38 10 -23, q and T is Kelvin temperature
+
+ 1.602
10 -19,
R4 2N2484 + U1A _ R1 10 k 15 V + U1B _ R3 -15V 270 k R2 10 k 2.5 M + U1C _ C1 R6 150 pF R5 10 k IC1 10 k + U1D _ VO (see equation above)
VI
NOTE A: U1A through U1D = TL05xA. IC1 = LM385, LT1004, or LT1009 voltage reference
Figure 87. Log Amplifier
-0.1 AVD - Differential Voltage Amplification - dB
-0.15
-0.2
-0.25
-0.3
-0.35
44
AA AA AA
-0.4 0 1 2 3 4 5 6 7 8 9 10 f - Frequency - Hz
Figure 88. Output Voltage vs Input Voltage for Log Amplifier
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION analog thermometer
By combining a current source that does not vary over temperature with an instrumentation amplifier, a precise analog thermometer can be built (see Figure 89). Amplifier U1A and IC1 establish a constant current through the temperature-sensing diode D1. For this section of the circuit to operate correctly, the TL05x must use split supplies, and R3 must be a metal-film resistor with a low temperature coefficient. The temperature-sensitive voltage from the diode is compared to a temperature-stable voltage reference set by IC2. R4 should be adjusted to provide the correct output voltage when the diode is at a known temperature. Although this potentiometer resistance varies with temperature, the divider ratio of the potentiometer remains constant. Amplifiers U1B, U2A, and U2B form the instrumentation amplifier that converts the difference between the diode and reference voltage to a voltage proportional to the temperature. With switch S1 closed, the amplifier gain equals 5 and the output voltage is proportional to temperature in degrees Celsius. With S1 open, the amplifier gain is 9 and the output is proportional to temperature in degrees Fahrenheit. Every time S1 is changed, R4 must be recalibrated. By setting S1 correctly, the output voltage equals 10 mV per degree (C or F).
IC1 C1 150 pF 100 k - R1 U1A + R3 10 k (see Note B) + U1B - R6 10 k R5 5 k R7 5 k S1 (see Note C) R9 10 k R12 10 k
+15 V - U2B + -15 V R11 10 k VO (see Note D) R10 10 k 45
D1 (see Note A)
+15 V R8 10 k - U2A IC2 R4 50 k +
R2
100 k
NOTES: A. B. C. D. E.
Temperature-sensing diode (-2 mV/C) Metal-film resistor (low temperature coefficient) Switch open for F and closed for C VO temperature; 10 mV/C or 10 mV/F U1, U2 = TL05x. IC1, IC2 = LM385, LT1004, or LT1009 voltage reference
Figure 89. Analog Thermometer
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION voltage-ratio-to-dB converter
The application in Figure 90 measures the amplitude ratio of two signals, then converts the ratio to decibels (see Figure 91). The output voltage provides a resolution of 100 mV/dB. The two inputs can be either dc or sinusoidal ac signals. When using ac signals, both signals should be the same frequency or output glitches will occur. For measuring two input signals of different frequencies, extra filtering should be added after the rectifiers. The circuit contains three low-offset TL05xA devices. Two of these devices provide the rectification and logarithmic conversion of the inputs. The third TL05xA forms an instrumentation amplifier. The stage performing the logarithmic conversion also requires two well-matched npn transistors. The input signal first passes through a high-impedance unity-gain buffer U1A (U2A). Then U1B (U2B) rectifies the input signal at a gain of 0.5, and U1C (U2C) provides a noninverting gain of 2, so that the system gain is still one. U1D (U2D), R6 (R13), and Q1 (Q2) perform the logarithmic conversion of the rectified input signal. The instrumentation amplifier formed by U3A, U3B, U3D scales the difference of the two logarithmic voltages by a gain of 33.6. As a result, the output voltage equals 100 mV/dB. The 1-k potentiometer on the input of U3C calibrates the zero-dB reference level. The following equations are used to derive the relationship between the input voltage ratio, expressed in decibels, and the output voltage.
X dB
+ 20 log + 8.686 + kT q
In
V V
A B
+ 20
A
In V
-V A B In (10)
X dB
In V V
- In V
B
V
BE(Q1)
A RI
V S
BE(Q2) kT q
+ kT q
A
V In R
B I
S
DVBE + VBE(Q1) -VBE(Q2) +
X dB where k
In V
- In V
B -V at 25C
+ 8.686 kT q
V
BE(Q1)
-V
BE(Q2)
+ 336
V
BE(Q1)
BE(Q2)
+ 1.38
10 -23, q
+ 1.602
10 -19, and T is Kelvin temperature
This gives a resolution of 1 V/dB. Therefore, the gain of the instrumentation amplifier is set at 33.6 to obtain 100 mV/dB.
46
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
R2 VA + U1A _ R1 20 k 10 k + U1B _ D1 2N2484 Q1
+ U1C _ R5 10 k R4 10 k
R6 10 k + U1D _ R7 10 k + U3A _ R16 16.3 k R18 10 k R20 10 k + U3D _ VO
R3 30 k R9 VB + U2A _ R8 20 k 10 k + U2B _ D2
2N2484
R76 16.3 k
+ U2C _ R12 10 k R11 10 k
R13 10 k + U2D _ R14 10 k
Q2 15 V
+ U3B _
R19 10 k R21 10 k + U3C _ C1
R10 30 k
82 k 1 k 82 k -15 V
NOTE A: U1A through U3D = TL05xA, VCC = 15 V. D1 and D2 = 1N914.
Figure 90. Voltage Ratio-to-dB Converter
2
VO - Output Voltage - V
1
0
-1
-2 0 1 2 3 4 5 6 Ratio - VA/VB 7 8 9 10
Figure 91. Output Voltage vs the Ratio of the Input Voltages for Voltage-to-dB Converter
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
47
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A - FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION macromodel information
Macromodel information provided was derived using Microsim Parts, the model-generation software used with Microsim PSpice. The Boyle macromodel (see Note 6 and subcircuit Figure 92) are generated using the TL05x typical electrical and operating characteristics at TA = 25C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D D D D D D
Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification
D D D D D D
Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers", IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 99 VCC+ RSS RP 2 IN- DP IN+ 3 11 RD1 VAD VCC- + - 4 C1 12 RD2 60 54 - VE .SUBCKT TL05x 1 2 3 4 5 C1 11 12 3.988E-12 C2 6 7 15.00E-12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX DP 4 3 DX EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 FB 7 99 POLY (5) VB VC VE VLP + VLN 0 2.875E6 -3E6 3E6 3E6 -3E6 GA 6 0 11 12 292.2E-6 GCM 0 6 10 99 6.542E-9 ISS 3 10 DC 300.0E-6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX R2 6 9 100.0E3 + OUT RD1 4 11 3.422E3 RD2 4 12 3.422E3 R01 8 5 125 R02 7 99 125 RP 3 4 11.11E3 RSS 10 99 666.7E6 VB 9 0 DC 0 VC 3 53 DC 3 VE 54 4 DC 3.7 VLIM 7 8 DC 0 VLP 91 0 DC 28 VLN 0 92 DC 28 .MODEL DX D (IS=800.0E-18) .MODEL JX PJF (IS=15.00E-12 BETA=185.2E-6 + VTO=-.1) .ENDS DE 5 RO1 DC J1 10 J2 3 9 ISS + VC R2 - 53 6 GCM + VB - C2 7 + GA VLIM 8 - - EGND + FB RO2 90 + DLP - 91 + VLP - DLN 92 - VLN +
HLIM
Figure 92. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
Macromodels, simulation models, or other models provided by TI, directly or indirectly, are not warranted by TI as fully representing all of the specification and operating characteristics of the semiconductor product to which the model relates.
48
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
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4-Jun-2007
PACKAGING INFORMATION
Orderable Device TL051ACD TL051ACDE4 TL051ACDG4 TL051ACP TL051ACPE4 TL051AID TL051AIP TL051CD TL051CDE4 TL051CDG4 TL051CDR TL051CDRE4 TL051CDRG4 TL051CP TL051CPE4 TL051ID TL051IDR TL051IP TL052ACD TL052ACDE4 TL052ACDG4 TL052ACDR TL052ACDRE4 TL052ACDRG4 TL052ACP TL052ACPE4 TL052AID Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOIC SOIC PDIP PDIP SOIC PDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC PDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SOIC Package Drawing D D D P P D P D D D D D D P P D D P D D D D D D P P D Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 75 75 75 75 75 75 75 75 75 50 50 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Call TI Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 75 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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4-Jun-2007
Orderable Device TL052AIDE4 TL052AIDG4 TL052AIDR TL052AIDRE4 TL052AIDRG4 TL052AIP TL052AIPE4 TL052AMFKB TL052AMJGB TL052CD TL052CDE4 TL052CDG4 TL052CDR TL052CDRE4 TL052CDRG4 TL052CP TL052CPE4 TL052CPSR TL052CPSRE4 TL052CPSRG4 TL052ID TL052IDE4 TL052IDG4 TL052IDR TL052IDRE4 TL052IDRG4 TL052IP
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC SOIC SOIC PDIP PDIP LCCC CDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SO SO SO SOIC SOIC SOIC SOIC SOIC SOIC PDIP
Package Drawing D D D D D P P FK JG D D D D D D P P PS PS PS D D D D D D P
Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 20 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 75 75 75 75 75 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 50 Pb-Free (RoHS) Pb-Free (RoHS)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 75 75 75 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 50 Pb-Free
Addendum-Page 2
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Orderable Device
Status (1)
Package Type PDIP LCCC CDIP CDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP LCCC CDIP SOIC SSOP SSOP SSOP SOIC
Package Drawing P FK JG JG D D D D D D N N D D D D D D N N FK J D DB DB DB D
Pins Package Eco Plan (2) Qty (RoHS) 8 20 8 8 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 20 14 14 14 14 14 14 50 50 50 50 50 Pb-Free (RoHS) TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
TL052IPE4 TL052MFKB TL052MJG TL052MJGB TL054ACD TL054ACDE4 TL054ACDG4 TL054ACDR TL054ACDRE4 TL054ACDRG4 TL054ACN TL054ACNE4 TL054AID TL054AIDE4 TL054AIDG4 TL054AIDR TL054AIDRE4 TL054AIDRG4 TL054AIN TL054AINE4 TL054AMFKB TL054AMJB TL054CD TL054CDBR TL054CDBRE4 TL054CDBRG4 TL054CDE4
ACTIVE OBSOLETE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
CU NIPDAU Call TI Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
N / A for Pkg Type Call TI Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Call TI Call TI Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 50 50 50 Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 50 Green (RoHS & no Sb/Br)
Addendum-Page 3
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Orderable Device TL054CDG4 TL054CDR TL054CDRE4 TL054CDRG4 TL054CN TL054CNE4 TL054CNSR TL054CNSRE4 TL054CNSRG4 TL054ID TL054IDE4 TL054IDG4 TL054IDR TL054IDRE4 TL054IDRG4 TL054IN TL054INE4 TL054MFKB TL054MJ TL054MJB
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE OBSOLETE
Package Type SOIC SOIC SOIC SOIC PDIP PDIP SO SO SO SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP LCCC CDIP CDIP
Package Drawing D D D D N N NS NS NS D D D D D D N N FK J J
Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 20 14 14 50 Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI Call TI Call TI
MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type Call TI Call TI Call TI
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 Pb-Free (RoHS) Pb-Free (RoHS)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 50 50 50 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 25 Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD TBD
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing SOIC SOIC SOIC SOIC SO SOIC SOIC SOIC SSOP SOIC SO SOIC D D D D PS D D D DB D NS D 8 8 8 8 8 8 14 14 14 14 14 14
SPQ
Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 330.0 12.4 12.4 12.4 12.4 16.4 12.4 16.4 16.4 16.4 16.4 16.4 16.4
A0 (mm)
B0 (mm)
K0 (mm)
P1 (mm) 8.0 8.0 8.0 8.0 12.0 8.0 8.0 8.0 12.0 8.0 12.0 8.0
W Pin1 (mm) Quadrant 12.0 12.0 12.0 12.0 16.0 12.0 16.0 16.0 16.0 16.0 16.0 16.0 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q1
TL051CDR TL052ACDR TL052AIDR TL052CDR TL052CPSR TL052IDR TL054ACDR TL054AIDR TL054CDBR TL054CDR TL054CNSR TL054IDR
2500 2500 2500 2500 2000 2500 2500 2500 2000 2500 2000 2500
6.4 6.4 6.4 6.4 8.2 6.4 6.5 6.5 8.2 6.5 8.2 6.5
5.2 5.2 5.2 5.2 6.6 5.2 9.0 9.0 6.6 9.0 10.5 9.0
2.1 2.1 2.1 2.1 2.5 2.1 2.1 2.1 2.5 2.1 2.5 2.1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device TL051CDR TL052ACDR TL052AIDR TL052CDR TL052CPSR TL052IDR TL054ACDR TL054AIDR TL054CDBR TL054CDR TL054CNSR TL054IDR
Package Type SOIC SOIC SOIC SOIC SO SOIC SOIC SOIC SSOP SOIC SO SOIC
Package Drawing D D D D PS D D D DB D NS D
Pins 8 8 8 8 8 8 14 14 14 14 14 14
SPQ 2500 2500 2500 2500 2000 2500 2500 2500 2000 2500 2000 2500
Length (mm) 340.5 340.5 340.5 340.5 346.0 340.5 333.2 333.2 346.0 333.2 346.0 333.2
Width (mm) 338.1 338.1 338.1 338.1 346.0 338.1 345.9 345.9 346.0 345.9 346.0 345.9
Height (mm) 20.6 20.6 20.6 20.6 33.0 20.6 28.6 28.6 33.0 28.6 33.0 28.6
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B - OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
1
2
3
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A - JANUARY 1995 - REVISED JUNE 1999
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
1
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MCER001A - JANUARY 1995 - REVISED JANUARY 1997
JG (R-GDIP-T8)
0.400 (10,16) 0.355 (9,00) 8 5
CERAMIC DUAL-IN-LINE
0.280 (7,11) 0.245 (6,22)
1
4 0.065 (1,65) 0.045 (1,14)
0.063 (1,60) 0.015 (0,38)
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN
0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20)
0-15
4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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